1. Field of the Invention
The present invention relates to a charge coupled device (hereinafter referred to as CCD), and more particularly, to the construction of a charge-voltage converting portion thereof.
2. Description of the Prior Art
Recently, CCD shift registers are widely used for solidstate image sensing devices and analog delay devices. For these devices, a method is frequently used where a serial of information is transferred after alternately allotted and inputted into two CCD analog shift registers for the purpose of reducing a picture element pitch and a driving frequency.
Generally, an output portion of the CCD is provided with a charge-voltage converting portion, where a signal charge transferred in the CCD is converted into a voltage which is in proportion to a charge quantity thereof and is taken out as an output signal after passing through an output amplifier.
In a case where the signal charge is inputted into two CCD shift registers and transferred, it is necessary to compose these two signals thereafter. It is desirable to compose the two signals before the signal charge is transferred to the charge-voltage converting portion. If the charge-voltage converting portion and an output amplifier were provided to an output portion of each shift register, since each charge-voltage converting portion and each output amplifier sometimes have different characteristics due to the difference in manufacturing dimension, the outputs of the two CCD shift registers might be different from each other.
FIGS. 1 and 2 show the arrangement of a conventional CCD where two CCD shift registers have a common charge-voltage converting portion. FIG. 1 shows a plane configuration thereof. FIG. 2 shows timing of clock pulses and an output signal.
As shown in FIG. 1, two CCD shift registers which are an A channel and a B channel are provided in this prior art. To form these CCD shift registers, for example, n-type semiconductor areas 1 and 2 are formed on a P-type silicon substrate. On upper portions of the semiconductor areas 1 and 2, a plurality of transfer electrodes 3, 4, 5 and 6 are provided through a gate insulating film such as an SiO2 film.
In the CCD shift registers, which employ a two-phase drive method, a clock pulse .phi.1 is applied to the transfer electrodes 3 and 6, and a clock pulse .phi.2 having a phase different from that of the clock pulse .phi.1 by 180.degree. is applied to the transfer electrodes 4 and 5. A barrier for deciding a transfer direction is formed at a lower portion of each transfer electrode by ion implantation of P-type impurity. The signal charge is transferred only from the right to the left through the lower portion of the transfer electrode and is not transferred from the left to the right therethrough.
The A channel and the B channel are coupled at an output electrode 7, and connected to a floating and diffusion layer 8. The floating and diffusion layer is connected to a reset drain 10 through a reset gate electrode 9. The floating and diffusion layer 8 and the reset gate electrode 9 are formed by diffusing n-type impurity into the P-type silicon substrate at a high density. The floating and diffusion layer 8, the reset gate electrode 9 and the reset drain 10 constitute a MOS (metal oxide semiconductor) transistor. That is, the reset drain 10, the floating and diffusion layer 8 and the reset gate electrode 9 function as a drain, a source and a gate of the MOS transistor, respectively.
The potential of the floating and diffusion layer 8 is directed out to an output terminal 22 through a conductive line 11 and a MOS transistor 12. For this reason, the conductive line 11 is connected to the gate of the MOS transistor 12. The source of the MOS transistor 12 is connected to an earth terminal 23 through a resistor 13 and to the output terminal 22. In this case, the MOS transistor 12 operates as a source follower amplifier.
A DC (direct current) voltage OG is applied to the output electrode 7, while a DC voltage RD is applied to the reset drain 10. Moreover, a DC voltage OD is applied to the drain of the MOS transistor 12 through a terminal 21. Further, a clock pulse .phi.R is applied to the reset gate electrode 9.
Subsequently, the operation of the above prior art will be described with reference to FIG. 2. When the level of the clock pulse .phi.R is high at t=t1, the potential of the floating and diffusion layer 8 is RD. When the level of the clock pulse .phi.R is low at t=t2, the floating and diffusion layer 8 is under a floating condition with respect to its potential. Then, the level of the clock pulse .phi.1 is low at t=t3, the signal charge of the A channel reaches the floating and diffusion layer 8 by way of a lower portion of the output electrode 7, and reduces the potential of the floating and diffusion layer 8 by discharging the junction capacitor of the floating and diffusion layer 8. Since the quantity of the potential reduction is in proportion to the signal charge quantity, the signal charge quantity is converted into a voltage.
Then, when the level of the clock pulse .phi.R is high again at t=t4, the potential of the floating and diffusion layer 8 is RD. When the level of the clock pulse .phi.R is low at t=t5, the floating and diffusion layer 8 is under the floating condition with respect to its potential. Then, when the level of the clock pulse .phi.2 is low at t=t6, the signal charge of the B channel reaches the floating and diffusion layer 8 by way of the lower portion of the output electrode 7, and reduces the potential of the floating and diffusion layer 8 by discharging the junction capacitor of the floating and diffusion layer 8.
By repeating the above-described operation, the signal charges of the A and B channels alternately reach the floating diffusion layer 8 and are converted into voltages. The potential of the floating and diffusion layer 8 is taken out as an output signal OS from the output terminal 22 by way of the source follower amplifier consisting of the MOS transistor 12.
Japanese laid-open Patent Application H2-91954 discloses a CCD where a plurality of transfer electrodes are further provided between the end terminal and the output terminal of each channel, and clock pulses .phi.3 and .phi.4 having frequencies higher than those of the clock pulses .phi.1 and .phi.2 are applied to the transfer electrodes and thereby the signal charge is transferred to the output terminal side.
As described above, signals of the two CCD shift registers can be composed before the signal charge is transferred to the charge-voltage converting portion. Thereby, it is enabled to obtain output signals produced by the same charge-voltage converting portion and by the same output amplifier.
Even with the arrangement of FIGS. 1 and 2, however, the signal of the A channel and that of the B channel are sometimes different, particularly, in the DC level. The cause thereof is considered as follows: after the floating and diffusion layer 8 is brought into the floating condition with respect to its potential, the signal charge of the A channel reaches the floating and diffusion layer 8 by the level down of the clock pulse .phi.1, while the signal charge of the B channel reaches the floating and diffusion layer 8 by the level down of the clock pulse .phi.2.
The floating and diffusion layer 8 is capacitance-coupled with the electrodes and conductive lines to which the clock pulse .phi.1 is applied and with the electrodes and conductive lines to which the clock pulse .phi.2 is applied through an aluminum shade or a silicon substrate provided on an upper portion of the CCD through an insulating layer. Because of this arrangement, the floating and diffusion layer 8 is induced by the clock pulses .phi.1 and .phi.2. Due to the limitation in pattern layout, it is difficult to make the two capacitance couplings completely identical. Moreover, concerning the clock pulses .phi.1 and .phi.2, it is also difficult to generate them by use of clock drivers having the same characteristics. For this reason, the induction received by the floating and diffusion layer 8 is different between at t=t2 and at t=5, so that a difference is caused in the DC level.
Moreover, the above-mentioned Japanese laid-open Patent Application H2-91954 also teaches that signal charges of two channels are composed and transferred by use of a common transfer electrode. However, when the clock pulse .phi.4 of the transfer electrode is activated, since the clock pulses .phi.1 and .phi.2 of each channel are also activated, the capacitance coupling of each channel is different from each other. Thereby, the output of the signal charge of each channel is different from each other in the DC level.